As is known, in VIPower (Vertical Intelligent Power) structures, i.e., power structures with vertical-current-flow control circuitry, the drive circuitry components are isolated using the junction isolation technique. FIG. 1 shows a cross section of a portion of a semiconductor material wafer 1 implementing a VIPower structure, and comprising an N.sup.++ type substrate 2, an N.sup.- type epitaxial layer 3, P-type buried layers 4, N-type dedicated wells 5, and P-type isolation regions 6. The P-type isolation regions 6 separate the N-type dedicated wells 5 and connect electrically to the buried layers 4 to form isolation wells 7. The N-type dedicated wells 5 house components of various types. For example, region LV to the right in FIG. 1 houses low-voltage MOS and/or bipolar components, and region HV to the left houses high-voltage power components.
As can be seen, as of surface 10 of the wafer, isolation wells 7 present an opposite type of conductivity to that of N-type dedicated wells 5, with which they define junctions which are reverse-biased to electrically isolate the various components and the power stage.
At present, the FIG. 1 structure is fabricated using the method described below with reference to FIGS. 2-9, wherein the regions common to FIG. 1 are indicated using the same numbering system. Additionally, for the sake of simplicity, the borders of superimposed layer portions of the same conductivity type and comparable doping level are only indicated, by dotted lines, in FIG. 1 relative to the step in which the region resulting in said superimposed layers is formed.
Commencing with substrate 2, a first N.sup.- type epitaxial layer 3a is grown. A P-type doping species is implanted and diffused to form buried layers 4 of the isolation wells and obtain the structure shown in FIG. 2. At this point, in the case of high or very high voltage structures in which high border efficiency is desired, a P-type doping species is implanted and diffused to form a P.sup.- type buried border ring 12 (FIG. 3) surrounding the high- and low-voltage regions close to the periphery of the device.
FIG. 4 illustrates an N-type doping species is implanted and diffused inside buried layers 4 to form buried regions 13 forming the bottom portion of N-type dedicated wells 5. A second epitaxial layer 3b is grown and a P-type doping species is implanted and diffused inside second epitaxial layer 3b, in such a position as to ensure electric continuity with buried layers 4, to form isolation regions 6 (FIG. 5). As shown in FIG. 5, the portions of second epitaxial layer 3b over buried regions 13 and laterally delimited by isolation regions 6 combine with buried regions 13 to form N-type dedicated wells 5 (FIG. 6).
At this point, border regions 14 are formed by implanting a small dose of a P-type doping species, which is diffused simultaneously with isolation regions 6. Border regions 14 surround the high-voltage and low-voltage regions, and, if buried rings 12 are provided, are superimposed on rings 12 to form a single deep high-resistivity structure 15 (FIG. 6). To improve the efficiency of structure 15, regions 14 are implanted using a doping species with a high coefficient of diffusion, such as aluminium. To obtain elaborate structures of variable resistivity, the VLD (Variation Lateral Doping) technique may also be used by appropriately designing the layout of the masks for forming regions 12 and 14.
FIG. 7 shows P-type dedicated wells 17 are formed by dedicated implantation and diffusion inside N-wells 5 to form components such as NPN or NMOS transistors. This step, instead of being performed after forming border structure 14 and isolation regions 6, may be performed straight after growing second epitaxial layer 3b.
Referring to FIG. 8, an N-type doping species is implanted or deposited and diffused inside N-wells 5 to form sinkers 18 for connecting buried regions 13.
The active areas of the components to be formed inside respective N-wells 5 and P-wells 17 are then defined (in a manner not shown). Deep body regions 20 and body regions 21 are implanted and diffused in dedicated manner inside N-wells 5 to form components such as NMOS, PMOS, NPN and PNP transistors. Finally, N-type regions 22 are formed by dedicated implantation and diffusion to complete the regions characterizing the MOS and bipolar components and the diffused regions of the power section, and so obtain the structure shown in FIG. 9. The power section (to the left) of the FIG. 9 structure presents an emitter switching ES type structure, comprising a high-voltage MOSFET and a bipolar component. The low-voltage section presents, from left to right, a PMOS transistor, a vertical or lateral PNP transistor, a lateral or vertical NPN transistor, and an NMOS transistor. Fabrication of the device is concluded with the formation of regions (such as gate regions, shown by the dashes in FIG. 9) on surface 10, definition of the contact areas and the relative metalization step.
At least as regards the bulk regions, the above sequence of steps for high-voltage devices is similar to the sequence for integrating low-voltage devices. Consequently, N.sup.++ type substrate 2 is not required for maintaining the voltage of the components defining the power stage, fabrication commences with a P-type substrate, and high-resistivity border structures 15 contiguous to the outermost isolation region 6 may be dispensed with.
The above method involves a large number of masking and implant steps, which, in addition to increasing fabrication cost, also endanger the efficiency and reliability of the device in the event of misalignment of the masks.